As artificial intelligence chips grow ever larger, the cost of a single manufacturing defect is rising dramatically — and the industry can no longer afford to treat yield loss as a rounding error.
Ahmad Khan, President of Semiconductor Products and Customer Group at KLA (NASDAQ: KLAC), drove that point home at the SEMICON Taiwan 2026 Masters Forum on September 2 with a stark illustration of how much chip economics have shifted. "If a wafer yields 1,000 small chips and one turns out defective, the impact on overall yield is negligible," he said. "But if that same wafer yields only five large AI chips and one is defective, yield instantly drops from 100% to 80%." Khan stressed the scenario was hypothetical — meant to show the relationship between die size and defect cost, not a description of current production norms — but the underlying message was clear: as chips approach the full size of the photolithographic reticle, every single defect carries far greater consequences for chipmakers and their customers alike.
AI Computing Power Has Soared 2,000-Fold in Just a Few Years
Khan opened by framing the sheer scale of AI's hardware demands. AI system computing power has grown roughly 2,000-fold in just a few years, he said, while memory bandwidth has expanded about 50-fold and chip-to-chip interconnect density has risen sharply. Linear scaling through Moore's Law is no longer enough to keep pace.
The industry's response has been to push computing architectures well beyond the traditional CPU, expanding into GPUs, matrix and vector processing units, high-bandwidth memory (HBM), and advanced packaging — all working in concert to boost parallel computing and data throughput. Khan also noted that the growth of AI inference markets will simultaneously lift demand for CPUs, DDR memory, and NAND flash. In his view, the old boundaries separating logic, memory, and packaging are dissolving, and future performance gains must be engineered at the full-system level from the start.
High-NA EUV, CFET and 3D DRAM Advance in Parallel
To sustain AI performance scaling, the semiconductor industry is pushing several technology frontiers at once. On the lithography side, the roadmap moves from 193nm immersion through extreme ultraviolet (EUV) to high numerical aperture EUV (High-NA EUV). Logic transistor architectures are evolving from gate-all-around (GAA) and backside power delivery toward complementary FETs (CFET). Memory architectures are extending from DDR and LPDDR into HBM, DRAM cell dimensions may shrink from 6F² toward 4F², and the long-term target is 3D DRAM. Advanced packaging, meanwhile, is advancing from fan-out and 2.5D/3D integration into wafer-to-wafer, die-to-wafer, and hybrid bonding.
Khan noted that each of these transitions brings new materials, new processes, and new defect signatures, forcing chipmakers to rebuild process windows and yield models from the ground up each time.
Oversized AI Packages Drive Industry Toward Square Panels
When full-reticle-sized compute dies are combined with multiple HBM stacks, the resulting package footprint can exceed what existing silicon interposers can handle. That constraint is pushing the industry to seriously evaluate panel-level packaging on larger, rectangular substrates. "We used to work exclusively with round wafers — now everyone is asking for square panels," Khan observed.
The shift, however, is anything but straightforward. Thin-film deposition uniformity, warpage control, and defect management all become significantly more complex at panel scale, requiring purpose-built equipment and entirely new metrology approaches.
Khan's closing argument was perhaps the most sobering: AI system yield can no longer be measured at the GPU level alone. When multiple high-value dies — GPU, DRAM, interposer, substrate, and packaging layers — are integrated into a single AI accelerator, a defect anywhere in that chain can render the entire assembly unusable. The economic stakes at every step of the manufacturing process have never been higher.
In Full
SEMICON Taiwan 2026 | KLA Warns One Defect Can Wipe Out 20% of Yield as AI Chips Near Reticle Limits
Original Article In Chinese
