Taiwan Semiconductor Manufacturing Company (TSMC) unveiled its next-generation process roadmap at its second-quarter 2026 earnings call on July 16, confirming that its A14 node will enter risk production in 2027 and full mass production in 2028 — even as the chipmaker manages near-term margin pressure from its ongoing 2-nanometer ramp.
Chairman and CEO C.C. Wei (魏哲家) said TSMC's 2nm process, known internally as N2, is now firmly in volume production and contributed roughly 3% of wafer revenue in the second quarter. The company said the N2 ramp is outpacing the early trajectory of its 3nm node, with customer adoption proceeding smoothly. Over the next five years, TSMC expects the number of new chip designs — known as tape-outs — committed to N2 to exceed equivalent counts for both 3nm and 5nm at comparable stages of their respective ramp cycles.
The earnings results come against a backdrop of what the company describes as strong, multi-year structural demand for AI chips. TSMC, the world's primary producer of advanced AI chips and a major supplier to Nvidia (NVDA), announced a further $100 billion expansion of its Arizona facilities, bringing total committed investment there to $265 billion. Despite record second-quarter results, the company's Taipei-listed shares fell 7.3% on July 18, reflecting investor caution over the sustainability of the AI infrastructure boom and the heavy capital outlays required to sustain growth.
TSMC Sets Three Hurdles for High NA EUV Adoption
One of the more closely watched topics at the earnings call was TSMC's timeline for deploying High NA EUV (High Numerical Aperture Extreme Ultraviolet) lithography equipment — the next-generation machines from Dutch manufacturer ASML that are widely seen as critical to scaling beyond current process nodes.
Wei declined to offer a specific timeline, reiterating what he described as TSMC's consistent, pragmatic approach. The company said it evaluates any new equipment against three criteria: whether the technology has reached sufficient maturity, whether it can sustain large-scale production at high yields, and — most critically — whether it delivers the cost-effectiveness that creates genuine value for customers.
"If a technology cannot balance cost and production capability, no matter how advanced it is, it is not something we will adopt right now," the company said. TSMC acknowledged that High NA EUV will be an important technology direction in the future, but emphasized that adoption timing will depend on a comprehensive assessment of product maturity, customer demand, and economic viability — not on being the first to use it.
A14 Family to Extend Through 2029 With Two Variants
On the A14 node itself, TSMC provided performance targets that position it as a meaningful leap over N2. At the same power budget, A14 is expected to deliver 10% to 15% better computational performance; at the same performance level, it can reduce power consumption by 25% to 30%. Logic density is projected to improve by roughly 20%. Like N2, A14 will target high-end applications in artificial intelligence, high-performance computing, and premium smartphones.
Wei also outlined two derivative nodes extending the A14 family through 2029. A13 will use Optical Shrink techniques to reduce chip die area by approximately 6% compared to A14. A12 will introduce Super Power Rail technology to improve on-chip power delivery efficiency. Both are targeted for mass production in 2029, giving the A14 family a three-node product line to serve varying customer requirements.
2nm Ramp Seen Diluting Gross Margins by Up to 7 Points
The accelerated 2nm build-out comes with a near-term financial cost. Senior Vice President and Chief Financial Officer Wendell Huang (黃仁昭) said the company expects the N2 capacity expansion — still in its production ramp phase — to weigh on gross margins by approximately three to four percentage points in the second half of 2026. Higher startup costs at overseas fabs, which carry heavier initial operating expenses than TSMC's home base in Taiwan, will add a further two to three percentage points of dilution.
Huang said the company expects these pressures to ease gradually as customer demand grows, production efficiency improves, and capacity across process generations is better optimized. The relief, however, will not come quickly. TSMC noted that from the time wafers begin production to when a customer's finished product reaches market, the typical lag is six to eight months — meaning revenue contributions from current N2 wafer starts will only begin to appear in reported figures later this year.
Wei Compares Foundry Switching to Buying Milk at a Convenience Store
Addressing the intensifying global semiconductor competition — including aggressive government subsidy programs that have helped rivals build new fab capacity — Wei pushed back on the notion that customers can easily shift manufacturing partners. Competitors including Samsung Electronics (005930.KS) and Intel (INTC) have been working to close the technology gap with TSMC, while the U.S. government has provided backing for domestic chipmaking initiatives.
"Many people assume that switching a wafer foundry is easy — but this is not like buying milk at a 7-Eleven," Wei said. "It is not something you do from one day to the next." Wei said customers typically require four to five years — sometimes longer — to fully transition to a new process node, moving from initial chip design and validation through risk production and eventual volume manufacturing. That accumulated investment and mutual trust, he argued, creates a partnership that government subsidies or competitor capacity expansions cannot quickly disrupt.
The deeper point, Wei said, is that the real determinant of competitive advantage in advanced chip manufacturing is not which company acquires the newest equipment first. It is which company can integrate equipment, process technology, yield management, cost controls, and customer design support into a platform capable of reliable, scalable mass production — and that, he said, is what has sustained TSMC's technology leadership over the long term.
TSMC also faces broader geopolitical headwinds. The company is reportedly facing a potential penalty of $1 billion or more related to a U.S. export control investigation over a chip it manufactured that was found inside a Huawei AI processor. Huang referred questions on the matter to the U.S. government but said the company's internal export control systems are continuously under review.
