Powerchip Semiconductor Manufacturing Corp. (PSMC) told investors on July 14 that it is capturing overflow demand from Taiwan Semiconductor Manufacturing Co.'s (TSMC) advanced packaging bottleneck, as chip stacking and interposer orders spill beyond the industry leader to other suppliers, including PSMC itself.
Speaking at an online earnings call, Chairman Frank Huang (黃崇仁) said the company's business no longer resembles the mature-node memory and logic foundry it built its name on. "Our company's structure is nothing like what it used to be," Huang said. "We are no longer a traditional mature-node foundry company." He pointed to silicon interposers, silicon capacitors, wafer-on-wafer (WoW) DRAM stacking, and a back-end wafer manufacturing partnership with Micron Technology as the pillars of that shift.
PSMC's newly created "3D AI Foundry" segment — which bundles interposers, integrated passive devices (IPD) and WoW stacking — accounted for 5.4% of second-quarter revenue, up from 3.2% in the first quarter, according to the company's earnings presentation. That is still far behind PSMC's core DRAM and logic foundry lines, but it is now the fastest-growing part of the business.
President Martin Chu said PSMC plans to ramp four product lines — interposers, silicon-capacitor IPD, Micron-linked wafer manufacturing (PWF) and WoW — over the next two years, with a goal of lifting the 3D AI Foundry share to 20% of revenue within three years to improve PSMC's product mix and profitability.
Hsinchu Cleanroom Space Constrains The Ramp
Chu acknowledged that customer demand is outpacing PSMC's physical capacity. Expansion is currently bottlenecked by limited cleanroom space at the company's Hsinchu fab. PSMC is relocating newer equipment from its Tongluo, Miaoli County plant to Hsinchu to replace older tools, while simultaneously reconfiguring production lines within its existing footprint — a process the company expects to continue through the end of 2027.
Interposer Orders Spill Over From TSMC's CoWoS Lines
PSMC's interposers feed into CoWoS-S and CoWoS-L, the advanced packaging platforms TSMC uses to stack AI chips such as Nvidia's. Even as TSMC keeps expanding CoWoS capacity, Chu said the market remains undersupplied, pushing some interposer orders toward alternative suppliers. PSMC previously moved its interposer back-end production line to Hsinchu as part of the Tongluo fab transaction; that line has now completed its restart and entered a ramp-up phase, taking on advanced-packaging orders.
Huang added that PSMC's decades of memory manufacturing have left it with capacitor-structure and process know-how it now wants to fold into interposers themselves, combining silicon capacitors with interposers for AI chip packaging and power-delivery applications. Those characterizations are management's own assessment from an earnings call rather than independently verified claims; how PSMC's technology actually stacks up against rivals will depend on customer qualification results, production scale and revenue contribution over time.
Silicon Capacitors Gain Traction In AI Power Delivery
As AI chips draw more power and dissipate more heat, packaging designers are looking for ways to place capacitance closer to the processor. Silicon capacitors, which are smaller and denser than traditional passive components, are one answer. Chu said PSMC now runs IPD and silicon-capacitor services on both 8-inch and 12-inch lines. Its 12-inch silicon capacitors have secured certification from a major international CPU maker for use with Embedded Multi-die Interconnect Bridge (EMIB) packaging and have entered stable production, currently shipping several thousand wafers a month. PSMC aims to push that to more than 10,000 wafers monthly by 2027 as AI-related customer projects multiply. Huang separately identified Intel (Nasdaq: INTC) as having certified PSMC's silicon capacitors for EMIB use. An 8-inch capacitor line, mainly serving optical communication modules, is already in mass production and is expected to see monthly demand in the thousands of wafers by 2027.
Wafer-On-Wafer DRAM Stacking Nears Customer Rollout
PSMC is also positioning WoW — which stacks DRAM and logic chips using hybrid bonding to shorten the distance signals travel between dies — as a core piece of its AI packaging strategy. Chu said the technology's high bandwidth, low power draw and compact footprint could eventually extend beyond high-performance computing into smart glasses, AR/VR headsets and AIoT devices.
Drawing on its existing DRAM wafer-stacking production experience, PSMC currently offers 4-layer and 8-layer stacks. Huang told analysts that 4-layer WoW has cleared certification with an advanced-process customer and meets the yield threshold for mass production, while trial output of the 8-layer version has topped a 90% yield. Both product lines' equipment has likewise been moved from Tongluo back to Hsinchu and restarted for small-batch trial runs. Huang said PSMC has spent roughly six years developing hybrid bonding and WoW technology and is now evaluating stacks with even more layers, arguing that denser vertical interconnects can raise bandwidth while cutting the power needed to move data — a potential efficiency lever for AI systems. Still, 4-layer output has not yet reached large-scale production, and the 8-layer product still needs to clear reliability testing and further customer validation, so the near-term revenue impact remains uncertain.
Micron Tie-Up Targets 2027 Mass Production
On the memory side, PSMC continues to build out PWF, a back-end wafer manufacturing service dedicated to Micron's (Nasdaq: MU) HBM production and a separate long-term arrangement that grew out of the Tongluo fab deal. Chu said a trial line, referred to internally as the "Mini Line," is on track to be completed by the end of 2026, with mass production targeted for the fourth quarter of 2027. Beyond a planned upgrade to PSMC's DRAM 1P process, PWF equipment and line construction will account for much of the company's capital spending over the next two to three years.
Taken together, PSMC's push into interposers, silicon capacitors, WoW stacking and Micron-linked wafer manufacturing amounts to a bet that its decades of memory and wafer-fabrication experience can translate into a foothold in AI advanced packaging. Whether the 3D AI Foundry segment can climb from 5.4% to 20% of revenue within three years will hinge largely on how quickly PSMC can finish reconfiguring its Hsinchu cleanroom space — and whether all four product lines win customer certifications on schedule and reach meaningful production volume. （Related： Taiwan's PSMC Raises Chip Prices as AI and Auto Demand Surge ｜ Latest ）
