Taiwan's Ennostar, TSMC Bet on Micro LED to Power Nvidia's AI Clusters

Co-packaged optical (CPO) interconnect technology was among the most closely watched themes at Computex 2026 in Taipei — a sign of how quickly the AI infrastructure industry is being forced to confront the physical limits of copper.

As generative AI drives data centers to operate at ever-greater scale, copper cabling's familiar weaknesses — signal attenuation, rising power draw, electromagnetic interference, and heat dissipation — are becoming harder to engineer around. The problem sharpens as switch speeds advance from 800G to 1.6T and now 3.2T. At those rates, moving data between GPUs with the low latency, high bandwidth, and minimal power consumption that large AI clusters require is simply beyond what copper can reliably deliver.

The industry response is a broad push toward fully optical, CPO-based interconnect architectures. Cloud service providers, GPU designers, and switch manufacturers are now treating this transition as a top-priority engineering challenge rather than a long-range roadmap item.

​Taiwan Semiconductor Manufacturing Co. (TSMC) used its 2026 Technology Forum to detail how its Compact Universal Photonic Engine — COUPE — will serve as the enabling platform for this transition, with volume production targeted for this year.

COUPE works by stacking a photonic integrated circuit and an electronic integrated circuit using TSMC's SoIC bonding technology, placing the resulting optical engine directly alongside the switch ASIC or GPU inside the package. TSMC has published claims of up to 10x lower latency and significant power efficiency gains over conventional pluggable optical modules on a board.

The platform's development has moved quickly. TSMC has progressed from small-form-factor pluggable qualification in 2025, to CoWoS interposer-based CPO integration achieving 115.2T aggregate bandwidth in the current generation of switches, toward the Rubin Ultra series expected in the first quarter of next year — which will bring optical interconnects to extremely close proximity inside processors and GPUs themselves.

The next major milestone driving this buildout is Nvidia's Feynman GPU architecture, expected to arrive in 2028. At GTC 2026, Nvidia confirmed that Feynman will mark the company's first full-scale deployment of CPO — integrating the optical engine directly onto the same substrate as the GPU, eliminating the need for separate pluggable modules.

At its core, the Feynman architecture will adopt 3.2T interconnects running at 400 gigabits per lane, operating through a full CPO framework. Critically for Taiwan's supply chain, Micro LED co-packaged optics are expected to make their commercial debut integrated within TSMC's COUPE manufacturing process in this generation. That prospect has set off a broad mobilization across the global Micro LED supply chain.

At the forefront of that mobilization is Ennostar (富采光電), the Taiwan-based optoelectronic semiconductor company formed through the merger of Epistar and Lextar, which completed in October 2025. Ennostar is widely regarded as one of the most advanced Micro LED developers globally, and its Chairman and President, Patrick Fan (范進雍), did not mince words about the company's direction.

"We are moving into optical communications not because we chose to, but because the market is demanding it, and we are working hard to develop accordingly," Fan said. The remark signals a clear shift: Micro LED in optical communications is no longer a research ambition but an approaching commercial reality.

Ennostar has already begun showcasing its Micro LED optical communication innovations in collaboration with AUO Corporation and Tyntek Corporation, presenting alongside VCSEL and continuous-wave distributed feedback laser diode (CW-DFB LD) solutions to address interconnect requirements across different transmission distances inside AI data centers.

The technical case for Micro LED in this application is built on a distinctive set of properties. Energy consumption comes in at just 1 to 2 picojoules per bit (pJ/bit), and the technology achieves a bit error rate (BER) as low as 10⁻¹⁰ — a level of signal integrity well-suited to the demanding conditions inside large-scale AI infrastructure.

Research firm TrendForce places Micro LED alongside Active Electrical Cables (AEC) and Vertical-Cavity Surface-Emitting Laser Near-Package Optics (VCSEL NPO) as one of three primary short-range, high-speed transmission solutions for intra-rack data center networks in scale-up architectures.

For the short distances — typically within 10 meters — that characterize connections inside a data center, Micro LED fits both CPO configurations and Active Optical Cable (AOC) high-speed interconnects. Additional advantages including high-temperature stability and an operational lifespan of up to 30,000 hours give it a meaningful edge over competing light-source technologies, with direct implications for reducing data center power consumption and cooling load.

Nvidia has already published its target specifications for next-generation silicon photonics CPO: energy consumption below 1.5 pJ/bit, density exceeding 0.5 terabits per second per square millimeter, and a reliability standard of fewer than 10 failures per billion device-hours (10 FIT).

Micro LED CPO meets those benchmarks. By integrating emitters of 50 micrometers or smaller with CMOS driver circuits, the technology delivers 1 to 2 pJ/bit — sitting comfortably within Nvidia's threshold and making it well-suited for the scale-up data center architectures Feynman will require.

Where conventional laser technologies pursue higher throughput by pushing individual channel speeds toward 100 Gbps, Micro LED takes a fundamentally different route: extreme emitter density packed into a minimal footprint.

Placing 800 individual Micro LED units — each 35 micrometers across, each capable of 2 Gbps — into a single square-millimeter chip delivers stable aggregate bandwidth of approximately 1.6 Tbps. Scaling the approach further, fitting 1,600 units of 25-micrometer emitters into the same chip area pushes that figure to 3.2 Tbps per square millimeter.

Arranging blue and green LED emissions in parallel extends bandwidth further still. Spatial division using multiple wavelengths or multiple channels can increase overall data throughput beyond what a single-color, single-channel configuration allows. Together, these techniques give Micro LED a credible path to meeting the density and efficiency demands of the AI data centers that Nvidia's Feynman generation is set to require.

​(Adapted from Wealth Invest Weekly, Issue 2407. By Lin Li-Hsueh )​

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