Arasan Chip Systems Announces Industry's First Sureboot™ Total 16-bit xSPI + PSRAM IP Solution

2026-05-28 23:15
Arasan Chip Systems Announces Industry's First Sureboot™ Total 16-bit xSPI + PSRAM IP Solution
Arasan Chip Systems Announces Industry's First Sureboot™ Total 16-bit xSPI + PSRAM IP Solution

Arasan Chip Systems Announces Industry's First Sureboot™ Total 16-bit xSPI + PSRAM IP Solution including support for AP Memory's Xccela™ PSRAM and the latest LVpSRAM™

SAN JOSE, Calif., May 28, 2026 /PRNewswire/ -- Arasan Chip Systems, a leading provider of IP for mobile and automobile SoC's, is proud to announce the launch of the industry's first Sureboot™ Total 16-bit xSPI + PSRAM IP. The Sureboot™ Total xSPI + PSRAM 16-bit IP includes the controller IP, seamlessly integrated PHY IP and software stack. This IP is specifically engineered to support AP Memory's Xccela™ PSRAM and their latest LVpSRAM™, providing a high-performance, low-power memory interface for next-generation SoC designs.

JEDEC xSPI + PSRAM IP Block Diagram
JEDEC xSPI + PSRAM IP Block Diagram

"Arasan and AP Memory have worked collaboratively with multiple customers over the years" said Jerry Hsueh, Senior Vice President at AP Memory. "We are pleased to see the latest PSRAM IP solution from Arasan supporting our latest line of PSRAM Devices, including the LVpSRAM™.

The Arasan Sureboot™ 16-bit xSPI PSRAM IP is a high-performance memory interface designed for maximum speed and flexibility, doubling standard throughput by using two 8-bit data lanes to transfer 32 bits every 266MHz clock cycle and supports 1.2v and 1.8v devices. It is fully compliant with the JEDEC JESD251C specification and backward compatible with Octal, Quad, and Dual SPI standards, ensuring it works with both modern and legacy devices. The IP simplifies system integration by booting directly into SPI mode for immediate memory access and features AXI memory mapping with built-in DMA support.

The Arasan Total IP Solution includes:

  • Sureboot™ 16-bit xSPI PSRAM Controller: A high-performance controller optimized for AP Memory's Xccela™ and LVpSRAM™, ensuring low latency and maximum throughput.
  • Compliant PHY: A robust physical layer (PHY) designed for high-speed signal integrity and seamlessly integrated with Arasan's xSPI Controller. Supports 1.2 v and 1.8v devices.
  • Complete Software Stack: A comprehensive firmware and software package to accelerate time-to-market and ensure seamless hardware-software synergy.

Arasan, a longstanding member of JEDEC offers a comprehensive portfolio of solid storage IP which includes Sureboot™ eMMC IP, SD Card IP, UFS IP, ONFI NAND Flash IP and standalone xSPI IP in addition to this PSRAM IP.

Availability
Arasan's Sureboot™ Total xSPI + PSRAM 16-bit IP with the PHY is available immediately on major foundries and on multiple nodes. Please contact sales@arasan.com to license the IP. 

For more product information, please visit:
https://www.arasan.com/product/xspi-nor-ip/

About Arasan
Arasan Chip Systems, founded in 1995 is a provider of IP solutions for mobile storage and connectivity interfaces. Arasan's focus lies in mobile SoCs, which have evolved to encompass a wide range of applications, from PDAs in the mid-'90s to today's automobiles, drones, and IoT devices. Arasan remains at the forefront of this "Mobile" evolution, providing standards-based IP that forms the foundation of Mobile SoCs. Over a billion chips have been shipped with Arasan's IP

About AP Memory
AP Memory (TWSE: 6531) is a global fabless design semiconductor company specializing in customized memory design and IP solutions. Products include IoT memory (IoTRAM™), AI memory solutions (VHM™), and silicon capacitors (S-SiCap™). With strong R&D capabilities, AP Memory is committed to providing high performance, low-power and innovative customized products and solutions for applications such as mobile communication, wearable, IoT, high-end mobile application, high-performance computing, and edge computing. (Related: VIVOTEK VORTEX Powers AI Cloud Security in Denmark's Kongens Ege Mixed-Use Development Latest

 

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